Description
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name VDD VSS MO1 MCK MLEN VDDA VSSA XTI X TO RSV RSV SO1 VSS2 VDD2 SO4 SO3 RSV VSS1 VDD1 SO2 RSV SO5 FSEL/MDT MO2 I/O
O Ip 1 Ip 1
I O
O
O O
Features
- s
PINOUT
(Top View)
s
s
s s s s
27 MHz master clock (internal PLL reference clock) Generated clocks.
- 27 MHz output.
- 33.8688 MHz output.
- 384fs output.
- 512fs output.
- 768fs output Sampling frequency fs.
- 44.1/48 kHz Output disable function Low jitter output: 100 ps (typ, 15pF load) Supply voltage: 3.3 V 24-pin VSOP package
VDD VSS MO1 MCK MLEN VDDA VSSA XTI XTO RSV RSV SO1
1
24
12
13
MO2 FSEL/MDT SO5 RSV SO2 VDD1 VSS1 RSV SO3 SO4 VDD2.