SM5921A Datasheet PDF - Nippon Precision Circuits 8-channel Lip Sync Delay Specs

SM5921A - 8-channel Lip Sync Delay

Datasheet Summary

Description

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Name VDD WCKI BCKI DIA DIB DIC DID XCS SCLK SI SIO TEST2 TEST3 DMUTEN RSTN VSS VDD TEST DOA DOB DOC DOD I/O 1 I I I I I I I I I Ot Id Id Ip Ip Id Ot Ot Ot Ot Supply pin Word clock input Bit clock input

Features

Functions I PINOUT (Top view) CASN RASN WEN CSN VDD 33 I I I I I I I I System clock input 64fs (fs = 32 to 192kHz) bit clock Sampling frequency: fs = 32 to 192kHz support Data input/output 3-wire serial, 8-channel PCM 64 clock/slot, word clock polarity inversion Direct mute function MCU interface: 3-wire serial Delay settings: sum of intrinsic delay and individual delay.
Intrinsic delay (common to all channels, default = 0 samples, 16-sample units).
Individual delay (ind.

Datasheet Details

Part number	SM5921A
Manufacturer	Nippon Precision Circuits
File Size	203.79 KB
Description	8-channel Lip Sync Delay
Datasheet	SM5921A Datasheet
Additional preview pages of the SM5921A datasheet.

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Full PDF Text Transcription

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SM5921A 8-channel Lip Sync Delay OVERVIEW The SM5921A is an SDRAM controller LSI for audio applications. It stores 64-fs slot 3-wire serial format audio data input at sampling frequency fs in SDRAM, and can access data at an arbitrary address to add a delay to each channel data. It also has a direct mute function to mute the audio data. www.DataSheet4U.

Published: Nov 9, 2008 |