N25Q128 Datasheet | Numonyx B.V

Features SPI-patible serial bus interface 108 MHz (maximum) clock frequency 2.7 V to 3.6 V single supply voltage Supports legacy SPI protocol and new Quad I/O or Dual I/O SPI protocol Quad/Dual I/O instructions resulting in an equivalent clock frequency up to 432 MHz: XIP mode for all three protocols - Configurable via volatile or non-volatile registers: enables Xi P mode directly after power on Program/Erase suspend instructions Continuous read (entire memory) via single instruction: - Fast Read - Quad or Dual Output Fast Read - Quad or Dual I/O Fast Read Flexible to fit application: - Configurable number of dummy cycles - Output buffer configurable - Fast POR instruction: decrease power-on time - Reset function (upon customer request) 64-byte user-lockable, one-time programmable (OTP) area Erase capability - Subsector (4-Kbyte) granularity in the 8 boot sectors (bottom or top parts) - Sector (64-Kbyte) granularity Write protections - Software write protection applicable to every 64-Kbyte sector (volatile lock bit) - Hardware write protection: protected area size defined by non-volatile bits (BP0, BP1, BP2, BP3 and TB bit) - Additional smart protections available upon customer request Electronic signature - JEDEC standard two-byte signature (BA18h) - Additional 2 Extended Device ID (EDID) bytes to identify device factory options - Unique ID code (UID) with 14 bytes read- only, available upon customer request More than 100,000 program/erase cycles per sector More than 20 years data retention Packages (all packages Ro HS pliant) - F8 = VDFPN8 8 x 6 mm (MLP8) - 12 = TBGA24 6 x 8 mm - F6 = VDFPN8 6 x 5 mm (MLP) - SF = SO16 (300 mils body width) - SE = SO8W (SO8 208 mils body width) July...