MG63P
DESCRIPTION
Oki’s 0.25 µm MG63P/64P/65P Application-Specific Integrated Circuit (ASIC) provides the ability to embed large blocks of Synchronous DRAM (SDRAM) into an embedded array architecture called the Customer Structured Array (CSA). Utilizing Oki’s leadership in DRAM technologies and wide experience of embedding SDRAM in logic products, Oki is able to integrate SDRAM and ASIC technology. The merged DRAM/ASIC process efficiently implements the Oki stacked capacitor memory cell. The MG63P/64P/65P CSA series uses three, four, and five metal process layers, respectively, on 0.25 µm drawn (0.18 µm L-effective) CMOS technology. The semiconductor process is adapted from Oki’s production-proven 64- Mbit DRAM manufacturing process. The 0.25 µm family provides significant performance, density, and power improvement over previous 0.30 µm and 0.35 µm technologies. An innovative 4-transistor cell structure provides 30 to 50% less power and 30 to 50% more usable gates than traditional cell...
