MG75P
Key Features
- Low 0.2µW/MHz/gate power dissipation
- User-configurable single- and dual-port memories
- Specialized IP cores and macrocells including 32-bit ARM7TDMI CPU, phase-locked loop (PLL), and peripheral ponent interconnect (PCI) cells
- Floorplanning for front-end simulation, backend layout controls, and link to synthesis
- Joint Test Action Group (JTAG) boundary scan and scan path Automatic Test Pattern Generation (ATPG)
- Support for popular CAE systems including Cadence, IKOS, Mentor Graphics, Model Technology, Inc. (MTI), Synopsys, and Viewlogic
