ML87V2103 Datasheet | OKI Electric

.Data Sheet.co.kr OKI Semiconductor ML87V2103 GENERAL DESCRIPTION PEDL87V2103DIGEST-01 Issue Date: Jan. 20, 2003 Preliminary Video Signal Noise Reduction and Rate Conversion IC with a Built-in 3.9 Mbit Field Memory The ML87V2103 prises a 3.9 Mbit field memory and logic circuits for signal processing and memory control. The device can reduce field-recursive noise and double the conversion speed. There is an automatic noise reduction mode that detects the noise level in the input video data to set the optimum noise reduction. There are two ways to double the conversion speed: progressive conversion that doubles the number of lines by doubling the horizontal direction frequency and flicker-free conversion that doubles both the vertical and horizontal direction frequencies. Features - Built-in memory: 3.9 Mbit filed memory × 1 unit - Maximum input operating frequencies (16 bits/8 bits, ITU-R BT.656): 14.75/29.5 MHz - Maximum output operating frequency: 29.5 MHz (double-speed conversion) - Power supply voltage : 3.3 V ± 0.3 V - Input pin: TTL-5V tolerant (5 V withstand voltage) - Input/output pins: Input TTL- output LVCMOS-5V tolerant (5 V withstand voltage) - Output pin: LVCMOS (3.3 V) - Input data format: YCb Cr (8 bits (Y) + 8 bits (Cb Cr)) (4:2:2) YCb Cr (8 bits (YCb Cr)) (4:2:2) ITU-R BT.656 (8 bits (YCb Cr)) - Output data format: YCb Cr (8 bits (Y) + 8 bits (Cb Cr)) (4:2:2) - Serial bus: I2C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps) - Internal memory controller: Input: patible with 625/50 Hz 2:1, 525/60 Hz 2:1 Output: patible with 625/50 Hz 2:1, 525/60 Hz 2:1, 625/50 Hz 1:1, 525/60 Hz 1:1, 625/100 Hz 2:1, 525/120 Hz 2:1 patible horizontal effective pixels: 640 (525 line mode only), 720, 768 - Sync generator (for output): Can generate sync signals of 625/50 Hz 2:1, 525/60 Hz 2:1, 625/50 Hz 1:1, 525/60 Hz 1:1, 625/100 Hz 2:1, 525/120 Hz 2:1. patible horizontal effective pixels: 640 (525 line mode only), 720, 768 - Field-recursive...