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MS81V04166 - Dual FIFO

General Description

The MS81V04166 is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation.

Key Features

  • 512 rows × 512 columns × 8 bits × 2 Fast FIFO (First-In First-Out) Operation: 25 ns cycle time Self refresh (No refresh control is required) High speed asynchronous serial access Read/Write Cycle Time 25 ns/30 ns/40 ns Access Time 23 ns/30 ns/35 ns www. DataSheet4U. com.
  • Variable length delay bit (600 to 262215).
  • Write mask function (Output enable control).
  • Cascading capability by mode setting.
  • Single power supply: 3.3 V ±10%.
  • Package: 100-Pin plastic T.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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PEDS81V04166-01 1 Semiconductor MS81V04166 Dual FIFO (262,214 Words × 8 Bits) × 2 This version: Dec. 2001 Preliminary GENERAL DESCRIPTION The MS81V04166 is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation. www.DataSheet4U.com The read clock of each of the 2Mb FIFO memories is connected in common, and the clocks are provided independently of each of the FIFO memories. The MS81V04166 functionally compatible with Oki’s 2Mb FIFO memory (MSM51V8222A), can be used as a ×16 configuration FIFO.