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MSM81C55 - 2048-Bit CMOS STATIC RAM

Description

The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer.

It uses silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum, while the chip is not selected.

Features

  • High speed and low power achieved with silicon gate CMOS technology.
  • 256 words x 8bits RAM.
  • Single power supply, 3 to 6 V.
  • Completely static operation.
  • On-chip address latch DataSheet4U. com.
  • 8-bit programmable I/O ports (port A and B).
  • TTL Compatible.
  • RAM data hold characteristic at 2 V.
  • 6-bit programmable I/O port (port C).
  • 14-bit programmable binary counter/timer.
  • Multiplexed address/data bus.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com E2O0014-27-X2 ¡ Semiconductor MSM81C55-5RS/GS/JS ¡ Semiconductor 2048-Bit CMOS STATIC RAM WITH I/O PORTS AND TIMER This version: Jan. 1998 MSM81C55-5RS/GS/JS Previous version: Aug. 1996 GENERAL DESCRIPTION The MSM81C55-5 has a 2k-bit static RAM (256 bytes) with parallel I/O ports and a timer. It uses silicon gate CMOS technology and consumes a standby current of 100 micro ampere, maximum, while the chip is not selected. Featureing a maximum access time of 400 ns, the MSM81C55-5 can be used in an MSM80C85AH system without using wait states. The parallel I/O consists of two 8-bit ports and one 6-bit port (both general purpose). The MSM81C55-5 also contains a 14-bit programmable counter/timer which may be used for sequence-wave generation or terminal count-pulsing.
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