• Part: MSM54V12222B
  • Description: FIELD MEMORY
  • Manufacturer: OKI Electric
  • Size: 157.93 KB
Download MSM54V12222B Datasheet PDF
OKI Electric
MSM54V12222B
MSM54V12222B is FIELD MEMORY manufactured by OKI Electric.
DESCRIPTION The OKI MSM54V12222B is a high performance 3-Mbit, 256K × 12-bit, Field Memory. It is especially designed for high-speed serial access applications such as HDTVs, conventional NTSC TVs, VTRs, digital movies and Multi-media systems. MSM54V12222B is a FRAM for wide or low end use in general modity TVs and VTRs exclusively. MSM54V12222B is not designed for the other use or high end use in medical systems, professional graphics systems which require long term picture storage, data storage systems and others. More than two MSM54V12222Bs can be cascaded directly without any delay devices among the MSM54V12222Bs. (Cascading of MSM54V12222B provides larger storage depth or a longer delay). Each of the 12-bit planes has separate serial write and read ports. These employ independent control clocks to support asynchronous read and write operations. Different clock rates are also supported that allow alternate data rates between write and read data streams. The MSM54V12222B provides high speed FIFO, First-In First-Out, operation without external refreshing: MSM54V12222B refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MSM54V12222B’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length, number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 256 × 12-bit enable high speed first-bitaccess with no clock delay just after the write or read reset timings. Additionally,...