Overview: SN74LS273 Octal D Flip-Flop with Clear
The SN74LS273 is a high-speed 8-Bit Register. The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset. This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.
http://onsemi.com • • • • 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES
Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current – High Output Current – Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 – 0.4 8.0 Unit V °C
20 mA mA 1 PLASTIC N SUFFIX CASE 738 20 1 SOIC DW SUFFIX CASE 751D ORDERING INFORMATION
Device SN74LS273N SN74LS273DW Package 16 Pin DIP 16 Pin Shipping 1440 Units/Box 2500/Tape & Reel © Semiconductor Components Industries, LLC, 1999 1 December, 1999 – Rev. 6 Publication Order Number: SN74LS273/D SN74LS273
CONNECTION DIAGRAM DIP (TOP VIEW)
VCC 20 Q7 19 D7 18 D6 17 Q6 16 Q5 15 D5 14 D4 13 Q4 12 CP 11 1 MR 2 Q0 3 D0 4 D1 5 Q1 6 Q2 7 D2 8 D3 9 Q3 10 GND LOADING (Note a) PIN NAMES CP D0 – D7 MR Q0 – Q7 Clock (Active HIGH Going Edge) Input Data Inputs Master Reset (Active LOW) Input Register Outputs HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. TRUTH TABLE
MR L H H CP X Dx X H L Qx L H L H = HIGH Logic Level L = LOW Logic Level X = Immaterial LOGIC DIAGRAM
3 11 4 7 8 13 14 17 18 D0 D1 D2 D3 D4 D5 D6 D7 CP CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q CP D CD Q 1 MR VCC = PIN 20 GND = PIN 10 = PIN NUMBERS Q0
2 Q1
5 Q2
6 Q3
9 Q4
12 Q5
15 Q6
16 Q7
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