ADP3212 Datasheet PDF (Mobile CPU Synchronous Buck Controller)

ADP3212 - Mobile CPU Synchronous Buck Controller

Description

Enable Input.

Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD and VRTT low, and pulls CLKEN high.

Good Output.

drain output.

A low logic state means that the output voltage is outside of the VID DAC defined range.

Current Monitor Output.

Features

Single.
Chip Solution.
Fully Compatible with the Intel® IMVP.
6.5t Specifications.
Selectable 1.
, 2.
, or 3.
Phase Operation with Up to 1 MHz per Phase Switching Frequency.
Phase 1 and Phase 2 Integrated MOSFET Drivers.
Input Voltage Range of 3.3 V to 22 V.
Guaranteed ±8 mV Worst.
Case Differentially Sensed.
Clock Enable Output Delays the CPU Clock Until the Core Voltage is Stable.

Datasheet Details

Part number	ADP3212
Manufacturer	ON Semiconductor
File Size	481.86 KB
Description	Mobile CPU Synchronous Buck Controller
Datasheet	ADP3212 Datasheet
Additional preview pages of the ADP3212 datasheet.

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Full PDF Text Transcription

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ADP3212, NCP3218, NCP3218G 7-Bit, Programmable, 3-Phase, Mobile CPU Synchronous Buck Controller The APD3212/NCP3218/NCP3218G is a highly efficient, multi−phase, synchronous buck switching regulator controller. With http://onsemi.com its integrated drivers, the APD3212/NCP3218/NCP3218G is optimized for converting the notebook battery voltage into the core supply voltage required by high performance Intel processors. An internal 7−bit DAC is used to read a VID code directly from the processor and to set the CPU core voltage to a value within the range 1 48 1 48 of 0.3 V to 1.5 V. The APD3212/NCP3218/NCP3218G is QFN48 QFN48 programmable for 1−, 2−, or 3−phase operation. The output signals CASE 485AJ CASE 485BA ensure interleaved 2− or 3−phase operation.

Published: Feb 11, 2010 |