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CAT24C04 - CMOS Serial EEPROM

Download the CAT24C04 datasheet PDF. This datasheet also covers the CAT24C01 variant, as both devices belong to the same cmos serial eeprom family and are provided as variant models within a single manufacturer datasheet.

General Description

The CAT24C02/04/08/16 are 2 Kb, 4 Kb, 8 Kb and 16

respectively I2C Serial EEPROM devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each.

All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol.

Key Features

  • Supports Standard and Fast I2C Protocol.
  • 1.7 V to 5.5 V Supply Voltage Range.
  • 16.
  • Byte Page Write Buffer.
  • Hardware Write Protection for Entire Memory.
  • Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs (SCL and SDA).
  • Low power CMOS Technology.
  • More than 1,000,000 Program/Erase Cycles.
  • 100 Year Data Retention.
  • Industrial and Extended Temperature Range.
  • These Devices are Pb.
  • Free,.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CAT24C01-ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CAT24C04
Manufacturer onsemi
File Size 213.92 KB
Description CMOS Serial EEPROM
Datasheet download datasheet CAT24C04 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
EEPROM Serial 2/4/8/16 Kb I2C CAT24C02, CAT24C04, CAT24C08, CAT24C16 Description The CAT24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb respectively I2C Serial EEPROM devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count.