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CAV24C04 - I2C CMOS Serial EEPROM

Download the CAV24C04 datasheet PDF. This datasheet also covers the CAV24C02 variant, as both devices belong to the same i2c cmos serial eeprom family and are provided as variant models within a single manufacturer datasheet.

General Description

The CAV24C02/04/08/16 are a EEPROM Serial 2/4/8/16

devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each.

All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol.

Key Features

  • Automotive AEC.
  • Q100 Grade 1 (.
  • 40C to +125C) Qualified.
  • Supports Standard and Fast I2C Protocol.
  • 2.5 V to 5.5 V Supply Voltage Range.
  • 16.
  • Byte Page Write Buffer.
  • Hardware Write Protection for Entire Memory.
  • CAV Prefix for Automotive and Other.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CAV24C02_ONSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number CAV24C04
Manufacturer onsemi
File Size 384.34 KB
Description I2C CMOS Serial EEPROM
Datasheet download datasheet CAV24C04 Datasheet

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Other Datasheets by onsemi

Part Number Description
CAV24C02 I2C CMOS Serial EEPROM
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CAV24C128 EEPROM
CAV24C16 I2C CMOS Serial EEPROM
CAV24C256 CMOS Serial EEPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
EEPROM Serial 2/4/8/16-Kb I2C - Automotive Grade 1 CAV24C02, CAV24C04, CAV24C08, CAV24C16 Description The CAV24C02/04/08/16 are a EEPROM Serial 2/4/8/16−Kb I2C devices organized internally as 16/32/64 and 128 pages respectively of 16 bytes each. All devices support both the Standard (100 kHz) as well as Fast (400 kHz) I2C protocol. Data is written by providing a starting address, then loading 1 to 16 contiguous bytes into a Page Write Buffer, and then writing all data to non−volatile memory in one internal write cycle. Data is read by providing a starting address and then shifting out data serially while automatically incrementing the internal address count.