Grade 1 device internally organized as 64Kx8 bits.
Key Features
a 128.
byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25512 device. The device features software and hardware write protection, including partial as well as full array protection. On.
Full PDF Text Transcription for CAV25512 (Reference)
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EEPROM Serial 512-Kb SPI Automotive Grade 1
CAV25512
Description The CAV25512 is a EEPROM Serial 512−Kb SPI Automotive
Grade 1 device internally organized as 64Kx8 bits. This features a 128−byte page write buffer and supports the Serial Peripheral Interface (SPI) protocol. The device is enabled through a Chip Select (CS) input. In addition, the required bus signals are clock input (SCK), data input (SI) and data output (SO) lines. The HOLD input may be used to pause any serial communication with the CAV25512 device. The device features software and hardware write protection, including partial as well as full array protection.
On−Chip ECC (Error Correction Code) makes the device suitable for high reliability applications.