CS5421 Datasheet | onsemi

features out- of- phase synchronization between the channels, reducing the input filter requirement. The CS5421 also provides undervoltage lockout, Soft Start, built in adaptive FET non- overlap and remote sense capability. The part is available in a 16 Lead SO Narrow package allowing the designer to minimize solution size. Features V2 Control Topology 150 ns Transient Response Programmable Soft Start 25 ns Gate Rise and Fall Times (with 1.0 n F load) 40 ns Adaptive FET Nonoverlap Time 100% Duty Cycle for Enhanced Transient Response Internal Slope pensation 1.0 V 0.8% and 2.0% Error Amplifier References 150 k Hz to 750 k Hz Programmable Frequency Operation Switching Frequency Set by Single Resistor Out- Of- Phase Synchronization Between the Channels Reduces the Input Filter Requirement - Undervoltage Lockout - On/Off Control Through Use of the P Pins http://onsemi. SO- 16 D SUFFIX CASE 751B PIN CONNECTIONS AND MARKING DIAGRAM GATE(H)1 GATE(L)1 PGND LGND SGND VFFB1 VFB1 P1 1 16 GATE(H)2 GATE(L)2 PGND2 VCC ROSC VFFB2 VFB2 P2 - - - - - - - - - - - CS5421 AWLYWW A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device CS5421GD16 CS5421GDR16 Package SO- 16 SO- 16 Shipping 48 Units/Rail 2500 Tape & Reel © Semiconductor ponents Industries, LLC, 2006 July, 2006 - Rev. 10 Publication Order Number: CS5421/D VIN 5.0 V VIN 12 V 1.0 μH 3 × 1200 μF VOUT 3.3 V/11 A 1.2 μH 15 4 × 1200 μF 14 11 9 0.1 μF 10 34.5 k 12 16 1.0 μF 13 VCC GATE(H)2 GATE(H)1 1 2.7 μH 3 × 1200 μF VOUT 1.5 V/9.0 A 6 × 1200 μF GATE(L)2 PGND2 VFFB2 P2 VFB2 ROSC LGND 4 GATE(L)2 2 3 6 8 0.1 μF PGND1 VFFB1 P1 SGND 5 VFB1 7 30 k 15 k GND SENSE 15 k 30.9 k Figure 1. Application Diagram, 5.0 V/12 V to 3.3 V/11 A and 1.5 V/9.0 A Converter for Processor I/O and Core Supplies ABSOLUTE MAXIMUM RATINGS- Rating Operating Junction Temperature, TJ Storage Temperature Range, TS ESD Susceptibility (Human Body Model) Package Thermal Resistance: Junction-...