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MC100E111 - 1:9 DIFFERENTIAL CLOCK DRIVER

General Description

designed with clock distribution in mind.

It accepts one signal input, which can be either differential or else single-ended if the VBB output is used.

The signal is fanned out to 9 identical differential outputs.

Key Features

  • Guaranteed Skew Spec.
  • Differential Design.
  • VBB Output.
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V.
  • Internal Input 50 KW Pulldown Resistors.
  • ESD Protection: > 3 kV Human Body Model.
  • Meets or Exceeds JEDEC Standard EIA/JESD78 IC Latchup Test.
  • Moisture Sensitivity: Level 3 (Pb-Free) (For Additional Information, see Ap.

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Datasheet Details

Part number MC100E111
Manufacturer onsemi
File Size 155.24 KB
Description 1:9 DIFFERENTIAL CLOCK DRIVER
Datasheet download datasheet MC100E111 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC10E111, MC100E111 5 V ECL 1:9 Differential Clock Driver Description The MC10E/100E111 is a low skew 1-to-9 differential driver, designed with clock distribution in mind. It accepts one signal input, which can be either differential or else single-ended if the VBB output is used. The signal is fanned out to 9 identical differential outputs. An enable input is also provided. A HIGH disables the device by forcing all Q outputs LOW and all Q outputs HIGH. The device is specifically designed, modeled and produced with low skew as the key goal. Optimal design and layout serve to minimize gate to gate skew within-device, and empirical modeling is used to determine process control limits that ensure consistent tpd distributions from lot to lot.