Description
explicitly for low skew clock distribution applications.
Features
- a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open in which case it will be pulled LOW by the input pulldown resistor) the SEL pin will select the
differential clock input. Both a common enable and individual output enables are provided. When asserted the positive output will go LOW on the next negative
transition of the CLK (or SCLK) input. The enabling function is synchronous so that the out.
MC100E211 Datasheet
