Datasheet Summary
5V ECL 3-Bit 4:1 Mux-Latch
The MC100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol).
When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
The 100 Series contains temperature pensation.
- 950 ps Max. D to Output
- 850 ps Max. LEN to Output
- Split Select
- Differential Outputs
- PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
- NECL Mode...
