MC100E336
Key Features
- The bus outputs also feature edge slow-down capacitors
- The Transmit Enable pins (TEN) control whether current data is held in the transmit register, or new data is loaded from the A/B inputs
- A LOW on both of the Bus Enable inputs (BUSEN), when clocked through the register, disables the bus outputs to -2.0 V
- The receiver section clocks bus data into the receive registers, after gating with the Receive Enable (RXEN) input
- All registers are clocked by a positive transition of CLK1 or CLK2 (or both)
