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MC100E452 - 5-BIT DIFFERENTIAL REGISTER

General Description

data (inputs and outputs) and clock.

The registers are triggered by a positive transition of the positive clock (CLK) input.

A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW.

Key Features

  • Differential D, CLK and Q; VBB Reference Available.
  • 1100 MHz Min. Toggle Frequency.
  • Asynchronous Master Reset.
  • PECL Mode Operating Range:.
  • VCC = 4.2 V to 5.7 V with VEE = 0 V.
  • NECL Mode Operating Range:.
  • VCC = 0 V with VEE =.
  • 4.2 V to.
  • 5.7 V.
  • Internal Input 50 kW Pulldown Resistors, Output Q3 will Default to Low State When Inputs Are Left Open.
  • ESD Protection:.
  • Human Body Model; > 2 kV.

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Datasheet Details

Part number MC100E452
Manufacturer onsemi
File Size 150.02 KB
Description 5-BIT DIFFERENTIAL REGISTER
Datasheet download datasheet MC100E452 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC10E452, MC100E452 5 V ECL 5‐Bit Differential Register Description The MC10E/100E452 is a 5-bit differential register with differential data (inputs and outputs) and clock. The registers are triggered by a positive transition of the positive clock (CLK) input. A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW. The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state.