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MC100LVEL51 - Differential Clock D Flip-Flop

Datasheet Summary

Description

The MC100LVEL51 is a differential clock D flip-flop with reset.

device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply.

Features

  • 475 ps Propagation Delay.
  • 2.8 GHz Toggle Frequency.
  • ESD Protection: > 4 kV Human Body Model, > 200 V Machine Model.
  • The 100 Series Contains Temperature Compensation.
  • PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V.
  • NECL Mode Operating Range: VCC = 0 V with VEE =.
  • 3.0 V to.
  • 3.8 V.
  • Internal Input Pulldown Resistors.
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test.
  • Moisture Sensit.

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Datasheet Details

Part number MC100LVEL51
Manufacturer ON Semiconductor
File Size 244.74 KB
Description Differential Clock D Flip-Flop
Datasheet download datasheet MC100LVEL51 Datasheet
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3.3 V ECL Differential Clock D Flip‐Flop MC100LVEL51 Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3 V VCC. The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
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