Overview: www.DataSheet4U.com MC10E160, MC100E160 5V ECL 12-Bit Parity Generator/Checker
The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS
1 28 • • • • • • • • Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900 ps Max. D to Q/Q Output Enable Asynchronous Register Reset Dual Clocks PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V Internal Input to 50 KW Pulldown Resistors Machine Model; > 7 V Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
PLCC−28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week MC10E160FN AWLYYWW 1 28 • • ESD Protection: Human Body Model; > 1 KV, • • Moisture Sensitivity Level 1 • • MC100E160FN AWLYYWW For Additional Information, see Application Note AND8003/D Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 Transistor Count = 312 devices ORDERING INFORMATION
Device MC10E160FN MC10E160FNR2 MC100E160FN MC100E160FNR2 Package PLCC−28 PLCC−28 PLCC−28 PLCC−28 Shipping † 37 Units/Rail 500 Units/Reel 37 Units/Rail 500 Units/Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2006 June, 2006 − Rev.
