Description
PIN D0
D2 S-IN LOAD SHIFT CLK MR S-OUT Q[0:2]a, Q[0:2]b Q[0:2]a, Q[0:2]b VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Scan Input ECL LOAD/HOLD Control ECL Scan Control ECL Clock ECL Reset ECL Scan Output ECL True Outputs ECL Inverting Outputs Positive Supply Negative Supply No Connect
FU
Features
- 1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020.
- ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire.
- OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Co.
MC10E212 Datasheet
