data (inputs and outputs) and clock.
The registers are triggered by a positive transition of the positive clock (CLK) input.
A high on the Master Reset (MR) asynchronously resets all registers so that the Q outputs go LOW.
| Part number | MC10E452 |
|---|---|
| Manufacturer | onsemi |
| File Size | 150.02 KB |
| Description | 5-BIT DIFFERENTIAL REGISTER |
| Datasheet |
 MC10E452 Datasheet
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| Part Number | Description | Manufacturer |
|---|---|---|
| MC10E452 | 5-BIT DIFFERENTIAL REGISTER | Motorola |
| MC10E451 | 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK | Motorola |
| MC10E457 | TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER | Motorola |
| MC10E404 | QUAD DIFFERENTIAL AND/NAND | Motorola |
| MC10E411 | 1:9 DIFFERENTIAL ECL/PECL RAMBUS CLOCK BUFFER | Motorola |
| Part Number | Description |
|---|---|
| MC10E451 | 6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK |
| MC10E457 | TRIPLE DIFFERENTIAL 2:1 MULTIPLEXER |
| MC10E404 | QUAD DIFFERENTIAL AND/NAND |
| MC10E411 | 5V ECL 1:9 Differential PECL/NECL RAMBus Clock Buffer |
| MC10E416 | QUINT DIFFERENTIAL LINE RECEIVER |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
