MC10EL34 Datasheet | onsemi

5 V ECL P2, P4, P8 Clock Generation Chip MC10EL34, MC100EL34 Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the mon output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 m F capacitor and limit current sourcing or sinking to 0.5 m A. When not used, VBB should be left open. The mon enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip- flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature pensation. Features - 50 ps Output-to-Output Skew - Synchronous Enable/Disable - Master Reset for Synchronization - PECL Mode Operating Range: - VCC = 4.2 V to 5.7 V with VEE = 0 V - NECL Mode Operating Range: - VCC = 0 V with VEE = - 4.2 V to - 5.7 V - Internal Input 75 k W Pulldown Resistors on CLK(s), EN, and MR - These Devices are Pb-Free, Halogen Free and are Ro HS pliant DATA SHEET .onsemi. 16 1 SOIC- 16 D SUFFIX CASE 751B- 05 MARKING DIAGRAMS- 10EL34G...