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MC10EP195, MC100EP195
3.3V ECL Programmable Delay Chip
The MC10/100EP195 is a Programmable Delay Chip (PDC)
designed primarily for clock deskewing and timing adjustment. It
provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and
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multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP195 has a digitally selectable resolution of about
MARKING
10 ps and a net range of up to 10.2 ns. The required delay is selected by
DIAGRAM*
the 10 data select inputs D[9:0] values and controlled by the LEN
(pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0].
MC10EP195 Datasheet
