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MC10EP35 - JK Flip Flop

General Description

EL35 JK flip-flop.

The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock.

Key Features

  • 410 ps Propagation Delay.
  • Maximum Frequency > 3 GHz Typical.
  • PECL Mode Operating Range:.
  • VCC = 3.0 V to 5.5 V with VEE = 0 V.
  • NECL Mode Operating Range:.
  • VCC = 0 V with VEE =.
  • 3.0 V to.
  • 5.5 V.
  • Open Input Default State.
  • Q Output Will Default LOW with Inputs Open or at VEE.
  • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www. onsemi. com 8 1 SOIC.
  • 8 NB D SUFFIX CASE 751.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MC10EP35, MC100EP35 3.3 V / 5 V ECL JK Flip‐Flop Description The MC10/100EP35 is a higher speed/low voltage version of the EL35 JK flip-flop. The J/K data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH. The 100 Series contains temperature compensation. Features • 410 ps Propagation Delay • Maximum Frequency > 3 GHz Typical • PECL Mode Operating Range: ♦ VCC = 3.0 V to 5.5 V with VEE = 0 V • NECL Mode Operating Range: ♦ VCC = 0 V with VEE = −3.0 V to −5.5 V • Open Input Default State • Q Output Will Default LOW with Inputs Open or at VEE • These Devices are Pb-Free, Halogen Free and are RoHS Compliant www.onsemi.