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MC14526B - Presettable 4-Bit Down Counters

Datasheet Summary

Description

Preset Enable (Pin 3)

If Reset is low, a high level on the Preset Enable input asynchronously loads the counter with the programmed values on P0, P1, P2, and P3.

A high level on the Inhibit input pre

vents the Clock from decrementing the counter.

Features

  • 50% 10% tTLH tTHL tPLH tf VDD.

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Datasheet Details

Part number MC14526B
Manufacturer ON Semiconductor
File Size 108.84 KB
Description Presettable 4-Bit Down Counters
Datasheet download datasheet MC14526B Datasheet
Additional preview pages of the MC14526B datasheet.

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Full PDF Text Transcription

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MC14526B Presettable 4-Bit Down Counters The MC14526B binary counter is constructed with MOS P–channel and N–channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded “0” state output for divide–by–N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide–by–N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.
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