MC74AC109 Datasheet | onsemi

MC74AC109, MC74ACT109 Dual JK Positive Edge- Triggered Flip- Flop The MC74AC109/74ACT109 consists of two high- speed pletely independent transition clocked JK flip- flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip- flop (refer to MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH - Outputs Source/Sink 24 mA - ′ACT109 Has TTL patible Inputs VCC CD2 J2 K2 CP2 SD2 Q2 Q2 16 15 14 13 12 11...