MC74HC597A Datasheet PDF (8-Bit Serial or ParallelInput/Serial-Output Shift Register)

MC74HC597A - 8-Bit Serial or ParallelInput/Serial-Output Shift Register

Description

Parallel data inputs.

Data on these inputs is stored in the input latch on the rising edge of the Latch Clock input.

SA (Pin 14) Serial data input.

Features

Output Drive Capability: 10 LSTTL Loads.
Outputs Directly Interface to CMOS, NMOS, and TTL.
Operating Voltage Range: 2.0 to 6.0 V.
Low Input Current: 1.0 mA.
High Noise Immunity Characteristic of CMOS Devices.
In Compliance with the Requirements Defined by JEDEC Standard No. 7A.
Chip Complexity: 516 FETs or 129 Equivalent Gates.
These are Pb.
Free Devices.
http://onsemi. com 16 1.

Datasheet Details

Part number	MC74HC597A
Manufacturer	ON Semiconductor
File Size	145.98 KB
Description	8-Bit Serial or ParallelInput/Serial-Output Shift Register
Datasheet	MC74HC597A Datasheet
Additional preview pages of the MC74HC597A datasheet.

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Full PDF Text Transcription

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MC74HC597A 8-Bit Serial or ParallelInput/Serial-Output Shift Register with Input Latch High−Performance Silicon−Gate CMOS The MC74HC597A is identical in pinout to the LS597. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of an 8−bit input latch which feeds parallel data to an 8−bit shift register. Data can also be loaded serially. The HC597A is similar in function to the HC589A, which is a 3−state device. Features • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No.

Published: Jan 18, 2016 |