MC74LCX158 Overview
S INPUTS OUTPUTS A0−A3 (Pins 2, 5, 11, 14) Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the LCX158. B0−B3 (Pins 3, 6, 10, 13) Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the LCX158. Y0−Y3 (Pins 4, 7, 9, 12) Data outputs. The selected input nibble is presented at these outputs when the Output Enable input is at a low level. The data present on these pins is in its inverted form for the LCX158. For the Output Enable input at a high level, the outpu
MC74LCX158 Key Features
- Designed for 2.3 to 3.6 V VCC Operation
- 5 V Tolerant Inputs
- Interface Capability With 5 V TTL Logic
- LVTTL patible
- LVCMOS patible
- 24 mA Balanced Output Sink and Source Capability
- Near Zero Static Supply Current (10 mA) Substantially Reduces
- Latchup Performance Exceeds 500 mA
- ESD Performance
- These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS
