Datasheet Summary
2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer
Description The NB3L208K is a differential 1:8 Clock fanout buffer with
High- speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single- ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides eight identical copies operating up to 350 MHz.
The NB3L208K is optimized for ultra- low phase noise, propagation delay variation and low output- to- output skew, and is DB800H pliant. As such, system designers can take advantage of the NB3L208K’s performance...