NB3L208K Description
The NB3L208K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4.
NB3L208K Key Features
- Maximum Input Clock Frequency > 350 MHz
- 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
- 8 HCSL Outputs
- DB800H pliant
- Individual OE Control Pin for Each Bank of 2 Outputs
- 100 ps Max Output-to-Output Skew Performance
- 1 ns Typical Propagation Delay
- 500 ps Typical Rise and Fall Times
- 80 fs Maximum Additive Phase Jitter RMS
- 40°C to +85°C Ambient Operating Temperature