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NB3L208K - 2.5V / 3.3V Differential 1:8 HCSL Fanout Buffer

General Description

The NB3L208K is a differential 1:8 Clock fanout buffer with High

speed Current Steering Logic (HCSL) outputs.

Inputs can directly accept differential LVPECL, LVDS, and HCSL signals.

ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference s

Key Features

  • Maximum Input Clock Frequency > 350 MHz.
  • 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation.
  • 8 HCSL Outputs.
  • DB800H Compliant.
  • Individual OE Control Pin for Each Bank of 2 Outputs.
  • 100 ps Max Output.
  • to.
  • Output Skew Performance.
  • 1 ns Typical Propagation Delay.
  • 500 ps Typical Rise and Fall Times.
  • 80 fs Maximum Additive Phase Jitter RMS.
  • 40°C to +85°C Ambient Operating Temperature.

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Datasheet Details

Part number NB3L208K
Manufacturer onsemi
File Size 125.94 KB
Description 2.5V / 3.3V Differential 1:8 HCSL Fanout Buffer
Datasheet download datasheet NB3L208K Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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NB3L208K 2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer Description The NB3L208K is a differential 1:8 Clock fanout buffer with High−speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS, and HCSL signals. Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external Vth reference supply per Figures 4 and 6. The input signal will be translated to HCSL and provides eight identical copies operating up to 350 MHz. The NB3L208K is optimized for ultra−low phase noise, propagation delay variation and low output–to–output skew, and is DB800H compliant.