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NB3N1200K - 3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer

Datasheet Summary

Description

The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point to

point clocks to multiple agents.

Features

  • 12 Differential Clock Output Pairs @ 0.7 V.
  • HCSL Compatible Outputs for NB3N1200K.
  • Low.
  • Power NMOS Push.
  • Pull Compatible Outputs for NB3W1200L.
  • Optimized 100 MHz and 133 MHz Operating Frequencies to Meet The Next Generation PCIe Gen2/Gen3/Gen4 and Intel QPI & UPI Phase Jitter.
  • DB1200Z and DB1200ZL Compliant.
  • 3.3 V ±5% Supply Voltage Operation.
  • Fixed.
  • Feedback for Lowest Input.
  • To.
  • Output Delay Vari.

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Datasheet Details

Part number NB3N1200K
Manufacturer ON Semiconductor
File Size 197.23 KB
Description 3.3V 100/133MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer
Datasheet download datasheet NB3N1200K Datasheet
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NB3N1200K, NB3W1200L 3.3 V 100/133 MHz Differential 1:12 HCSL or Push-Pull Clock ZDB/Fanout Buffer for PCle Description The NB3N1200K and NB3W1200L differential clock buffers are DB1200Z and DB1200ZL compliant and are designed to work in conjunction with a PCIe compliant source clock synthesizer to provide point−to−point clocks to multiple agents. The device is capable of distributing the reference clocks for Intel® QuickPath Interconnect (Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI) applications. The VCO of the device is optimized to support 100 MHz and 133 MHz frequency operation. The NB3N1200K and NB3W1200L utilize pseudo−external feedback topology to achieve low input−to output delay variation.
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