NB4N11M- Multi Level Clock/Data Input to CML Receiver/Buffer/Translator
Full PDF Text Transcription
Click to expand full text
NB4L339
2.5 V / 3.3 V Differential 2:1
Clock IN to Differential
LVPECL Clock Generator /
Divider / Fan-Out Buffer
Multi−Level Inputs w/ Internal Termination
Description The NB4L339 is a multi−function Clock generator featuring a 2:1
Clock multiplexer front end and simultaneously outputs a selection of four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8. One divide block has a choice of ÷1 or ÷ 2.
The output of each divider block is fanned−out to two identical differential LVPECL copies of the selected clock. All outputs provide standard LVPECL voltage levels when externally terminated with a 50−ohm resistor to VCC − 2 V.
The differential Clock inputs incorporate internal 50−W termination resistors and will accept LVPECL, CML or LVDS logic levels.
NB4L339 Datasheet
