NB7L14M Description
MARKING DIAGRAM 16 1 The NB7L14M is a differential 1−to−4 clock/data distribution chip with internal source terminated CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively. As such, NB7L14M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications.
NB7L14M Key Features
- Rev. 1
- LVPECL, CML, LVCMOS, LVTTL, LVDS LVPECL, CML, LVCMOS, LVTTL, LVDS
- Power Supply CML Output CML Output Power Supply CML Output CML Output CML Output CML Output CML Output CML Output
- Internal 50 W Termination Pin for CLK. Inverted Differential Clock/Data Input. (Note 1) Description