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NIS1050 - Protection Interface

Datasheet Summary

Description

This is the source of the power FET and connects to the PMIC pin of the same name.

This pin is the gate of the FET switch.

Positive input voltage to the device.

Features

  • Lower Power Dissipation and Higher Efficiency vs. Zener Shunt Regulator.
  • LDO Highly Stable across Temperature, Operates Without Bypass Capacitors.
  • Wide 3-30 V Power Supply Voltage Input Range.
  • Low.
  • Profile (0.75mm) 6-Lead 2x2mm WDFN6 Package.
  • This is a Pb.
  • Free Device Typical.

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Datasheet preview – NIS1050

Datasheet Details

Part number NIS1050
Manufacturer ON Semiconductor
File Size 183.84 KB
Description Protection Interface
Datasheet download datasheet NIS1050 Datasheet
Additional preview pages of the NIS1050 datasheet.

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Full PDF Text Transcription

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NIS1050 Protection Interface Circuit for PMICs with Integrated OVP Control The NIS1050 is a protection IC targeted at the latest generation of PMICs from the leading mobile phone and UMPC chipset vendors. It includes a highly stable low-current LDO and a low impedance power N-Channel MOSFET. The LDO provides a low current, five volt supply to the PMIC, and the NFET is the external pass element for the OVIC circuit. These stages combine with the internal PMIC to protect the charging circuit from low-impedance overvoltage conditions that can occur from either the AC/DC or USB supply. The NIS1050 is available in the low−profile 6-lead 2x2mm WDFN6 surface mount package. Features • Lower Power Dissipation and Higher Efficiency vs.
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