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P3P85R01A - 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device

Description

TIMING SAFE Peak EMI reduction device.

TIMING SAFE technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path.

Refer to Figure 3.

Features

  • 1x, LVCMOS Peak EMI Reduction.
  • Input Frequency Range: 75 MHz.
  • 200 MHz.
  • Output Frequency Range: 75 MHz.
  • 200 MHz.
  • Analog Deviation Selection.
  • Analog Input.
  • Output Delay Control.
  • Analog PLL Output Delay Control.
  • Low Cycle.
  • to.
  • Cycle Jitter.
  • Supply Voltage: 3.3 V ± 0.3 V.
  • 8 pin, WDFN, 2 mm x 2 mm (TDFN) Package.
  • Operating Temperature Range: 0°C to +70°C.
  • These De.

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Datasheet Details

Part number P3P85R01A
Manufacturer ON Semiconductor
File Size 135.57 KB
Description 75 MHz to 200 MHz LVCMOS TIMING SAFE Peak EMI Reduction Device
Datasheet download datasheet P3P85R01A Datasheet
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P3P85R01A 3.3V, 75 MHz to 200 MHz LVCMOS TIMING SAFE] Peak EMI Reduction Device Functional Description P3P85R01A is a versatile, 3.3 V, LVCMOS, wide frequency range, TIMING SAFE Peak EMI reduction device. TIMING SAFE technology is the ability to modulate a clock source with Spread Spectrum technology and maintain synchronization with any associated data path. Refer to Figure 3. P3P85R01A has an SSEXTR pin that selects different frequency deviations depending upon the value of the resistor connected between this pin and GND. P3P85R01A has a DLY_CTRL pin used for adjusting the Input-Output clock delay, depending upon the value of capacitor connected at this pin to GND. The DLY_CTRL output phase is complementary to that of ModOUT clock. This signal enables better EMI management.
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