NL27WZ125
Key Features
- Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5 V Designed for 1.65 V to 5.5 V VCC Operation Over Voltage Tolerant Inputs and Outputs LVTTL patible - Interface Capability With 5 V TTL Logic with VCC = 3 V LVCMOS patible 24 mA Balanced Output Sink and Source Capability Near Zero Static Supply Current Substantially Reduces System Power Requirements 3-State OE Input is Active-Low Replacement for NC7WZ125 Chip plexity = 72 FETs
