MC100E210 Overview
Key Features
- two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip
- The device features fully differential clock paths to minimize both device and system skew
- This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task
- This shift is about 10-20 pS in TPD
- The skew between any two output pairs within a device is typically about 25 nS
- If other output pairs are not terminated, the lowest TPD d
