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82C621A - PCI IDE Controller

Datasheet Summary

Description

Figure 3-1 Pin Diagram .~ a:: rn !c- -z

Features

  • Supports 32-bit PCI Bus & Configuration Registers 100-pin PQFP Supports 4 ATA peripherals Optional PCI Expansion ROM support 16-byte Read-Prefetch and Write-Posting FIFO IDE timing controlled by either Straps or Registers 2.1 Special Feature Notes Write Posting and Read-prefetch allows CPU memory cycles to run concurrently with IDE cycles and also removes the synchronization penalty for AT-bus transfers. IDE cycles can be fine tuned by the ANSI Mode strap options or programmable registers for A.

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Datasheet Details

Part number 82C621A
Manufacturer OPTi
File Size 1.04 MB
Description PCI IDE Controller
Datasheet download datasheet 82C621A Datasheet
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82C621A PCI IDE Controller 1.0 Overview The OPTi 82C621A PCI IDE Controller (PIC) is a 100-pin controller chip designed for a fast and flexible interface between the PCI bus and two IDE cables. The 82C621A implements a PCI function to directly support both the Primary and Secondary IDE in a single 100-pin PQFP. This high-integration approach reduces component count, eases board design, reduces cost and increases reliability. An integrated 4-level read-prefetch FIFO and a 4-level posted write FIFO supports zero wait-state operations, substantially improving performance over other IDE implementations. The Enhanced ATA Specification can be supported either by setting Strap Options or by programming internal registers. 2.
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