MC8051 Datasheet | Oregano

Overview Key Features Fully synchronous design Instruction set patible to the industry standard 8051 microcontroller Optimized architecture enables fast one to four clocks per OP code Up to 10 times faster due to pletely new architecture User selectable number of timers/counters as well as serial interface units Active timer/counter and serial interface units selectable via additional special function register Optional implementation of the multiply mand (MUL) using a parallel multiplier unit Optional implementation of the divide mand (DIV) using a parallel divider unit Optional implementation of the decimal adjustment mand (DA) No multiplexed I/O ports 256 bytes internal RAM Up to 64 Kbytes ROM and up to 64 Kbytes RAM Source code available free of charge under the GNU LGPL license Technology independent, clear structured, well mented VHDL source code Easily expandable by adapting/changing VHDL source code Parameterizeable via VHDL constants page 2 of 11 .. 8051 IP Core - Block Diagram The starting from the top level module and its submodules are depicted in figure 1. The toplevel signal names are shown as well as the three memory blocks used in the design. The user selectable number of serial interfaces and timer/counter units is indicated by the dotted line between the modules mc8051_siu and mc8051_tmrctr. clk reset all_t0_i all_t1_i all_rxd_i int0_i int1_i p0_i p1_i p2_i p3_i N N mc8051_siu mc8051_siu N N N all_rxdwr_o all_txd_o all_rxd_o N mc8051_alu N N mc8051_tmrctr mc8051_tmrctr 8 8 8 8 8 8 8 8 p0_o p1_o p2_o p3_o mc8051_control mc8051_core mc8051_top mc8051_ram (128x8 bit) mc8051_rom (up to 64kx8 bit) mc8051_ramx (up to 64kx8 bit) figure 1: Block diagram of the 8051 microcontroller IP-core. page 3 of 11 .. Signal Name clk reset all_t0_i all_t1_i all_rxd_i int0_i int1_i p0_i p1_i p2_i p3_i all_rxdwr_o all_txd_o all_rxd_o p0_o p1_o p2_o p3_o Description System clock. Only rising edge used. Asynchronous reset of all flip-flops....