PEX8111 Datasheet | PLX Technology

Features - General Features o Forward and Reverse bridging o Tiny 161 ball BGA package (10mm x 10mm) o Low power - 0.3 Watts maximum o EEPROM configuration option with SPI o Internal 8Kbyte shared RAM o 1.5 V core supply voltage o JTAG o Four (4) GPIO pins for maximum design and application flexibility o Extensive PME support including D0 and D0Active, D1, D2 and D3Hot and D3Cold - Integrated PCI Express Interface o PCI Express Base specification 1.0a pliant o x1 Link, full-duplex, 2.5 Gbps o One virtual channel o Automatic LVDS polarity reversal o 128 byte maximum payload size o Link CRC o Link power management o Flow control buffering o PCI Express transaction queues for eight (8) outstanding TLPs - PCI Interface o PCI 3.0: 32 bits at 33 MHz o PCI Power Management 1.1 o Internal arbiter supports up to 4 external masters; provides REQ#/GNT# signals o 3.3V I/O and 5V tolerant PCI o Message Signal Interrupt (MSI) support o Provides PCI clock output o Four mailbox registers for messaging o ISA Enable and VGA Enable registers for legacy operation PCI Express to PCI Bridge Reversible Bridge in a Tiny Package The PLX Technology PEX 8111 bridge enables designers to migrate legacy PCI bus interfaces to the new advanced serial PCI Express. This is ideal when including existing PCI ICs on a PCI Express™ Adapter Board, such as the new Express Card™ standard. This simple bridge can also reside on either end of a PCI Express cable to connect remote functions running the PCI protocol. The PEX 8111 supports forward and reverse bridging. The tiny 10 mm x 10mm Plastic BGA package makes the PEX 8111 bridge ideal for use in applications where board real estate is at a premium. With its low power 0.15 micron CMOS design, the PEX 8111 consumes a maximum power of only 300 m W. Forward and Reverse Bridging pliant to the PCI Express-to-PCI/PCI-X Bridge Specification 1.0, the PEX 8111 is capable of operating in either forward or reverse bridging modes. In forward mode, the bridge...