Datasheet4U Logo Datasheet4U.com

PEX8111 - PCI Express to PCI Bridge

Description

DataSheet4U.com © 2004 PLX Technology, Inc.

All rights reserved.

Features

  • PCI Host CPU PCI Bus PEX 8111 PCI-to-PCI Express Bridge PEx ASIC Figure 3. Reverse Bridge with PCI CPU Product Ordering Information PLX Technology, Inc. 870 Maude Ave. Sunnyvale, CA 94085 USA Tel: 1-800-759-3735 Tel: 1-408-774-9060 Fax: 1-408-774-2169 Email: info@plxtech. com Web Site: www. plxtech. com Part Number PEX 8111-AA33BC PEX 8111RDK-F PEX 8111RDK-R.

📥 Download Datasheet

Datasheet preview – PEX8111

Datasheet Details

Part number PEX8111
Manufacturer PLX Technology
File Size 382.81 KB
Description PCI Express to PCI Bridge
Datasheet download datasheet PEX8111 Datasheet
Additional preview pages of the PEX8111 datasheet.

📁 Similar Datasheet

  • PEX8111 - PEX8111 / PEX8114 (ETC)
  • PEX8111 - Rapid Development Kit (Paltek)
  • PEX8114 - PEX8111 / PEX8114 (ETC)
  • PEX8516 - Flexible & Versatile PCI Express Switches (PLX)
  • PEX8532 - Flexible & Versatile PCI Express Switches (PLX)
  • PEX8533 - Flexible & Versatile PCI Express Switches (PLX)
  • PEX8624 - PCI Express switching (PLX)
Other Datasheets by PLX Technology
  • PEX8114 - PCI Express to PCI Bridge
  • PEX8311 - ExpressLane PCI Express to Generic Local Bus Bridge

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com . Version 1.0 2004 PEX 8111 Features ƒ General Features o Forward and Reverse bridging o Tiny 161 ball BGA package (10mm x 10mm) o Low power – 0.3 Watts maximum o EEPROM configuration option with SPI o Internal 8Kbyte shared RAM o 1.5 V core supply voltage o JTAG o Four (4) GPIO pins for maximum design and application flexibility o Extensive PME support including D0 and D0Active, D1, D2 and D3Hot and D3Cold ƒ Integrated PCI Express Interface o PCI Express Base specification 1.0a compliant o x1 Link, full-duplex, 2.5 Gbps o One virtual channel o Automatic LVDS polarity reversal o 128 byte maximum payload size o Link CRC o Link power management o Flow control buffering o PCI Express transaction queues for eight (8) outstanding TLPs ƒ PCI Interface o PCI 3.
Published: |