PM5309 Datasheet | PMC-Sierra

FEATURES - High performance backplane interface and cross-connect for 2.5G line cards in SONET/SDH systems. - Provides one low-speed parallel Tele Bus interface operating at 32 bits x 77.76 MHz. - Provides three high-speed multi-rate serial backplane interfaces. - Supports CLOS and memory-based switch fabric systems. - Supports linear, UPSR, and BLSR protection strategies. - Provides two pages of connection memory with software and hardware controlled hitless page swaps at frame boundaries. - Provides integrated delay management that allows for arbitrary SONET/SDH frame alignments on each ingress serial link. - High-speed serial RASIO patible with CML, LVDS, and LVPECL. - Supports nibble and di-bit slicing on 622 Mbit/s links for sliced switching architectures. PARALLEL PORT FUNCTIONS - Supports one 32-bit or four 8-bit 77.76 MHz Tele Bus interfaces to SERIAL PORT FUNCTIONS interface with parallel Tele Bus - Supports three RASIO 3G high-speed framers and mappers. serial backplane interfaces for interfacing - Integrated pointer interpreter reduces with SONET/SDH cross-connects, plexity of external framers and framers, mappers, and other mappers by asserting payload, J0, and TBS™ 2488 devices. J1 indications on the outgoing SWITCHING CAPACITY - Each high-speed serial backplane Tele Bus interface. - Implements a 10G memory switch fabric interface is capable of independent - Allows insertion and extraction of TOH with STS-1/AU-3 switching granularity in operation at 4x622 Mbit/s scrambled bytes through a dedicated low speed a single device. NRZ SONET/SDH, 4x777 Mbit/s Serial serial interface. - Supports non-blocking anycast switching Tele Bus, or 1x2488 Mbit/s between any of the serial or parallel scrambled NRZ SONET/SDH. interfaces. BLOCK DIAGRAM Rx P1[4:1] Rx N1[4:1] Rx RASIO ESSI Link Framing & Monitoring Pointer Interpreter & Delay Mgmt ESSI Link Generator Tx RASIO Tx P1[4:1] Tx N1[4:1] Rx P2[4:1] Rx N2[4:1] Rx RASIO STS-1 / AU-3 Cross-Connect ESSI Link Framing &...