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PM7388 - Frame Engine and Datalink Manager

This page provides the datasheet information for the PM7388, a member of the PM7388_PMC Frame Engine and Datalink Manager family.

Features

  • Single-chip multi-channel packet processor supporting line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 336 T1s, 252 E1s, or 12 DS-3s.
  • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. configurable on a per multilink bundle. Optionally full packet transfers are suppor.

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Datasheet preview – PM7388

Datasheet Details

Part number PM7388
Manufacturer PMC-Sierra
File Size 58.48 KB
Description Frame Engine and Datalink Manager
Datasheet download datasheet PM7388 Datasheet
Additional preview pages of the PM7388 datasheet.

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Full PDF Text Transcription

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Preliminary PM7388 FREEDM 336A1024 Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 336 T1s, 252 E1s, or 12 DS-3s. • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. • Supports up to 168 multilink bundles with up to 12 member links per bundle. These bundles are composed of independent HDLC channels.
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