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PM7389 - Frame Engine and Datalink Manager

This page provides the datasheet information for the PM7389, a member of the PM7389_PMC Frame Engine and Datalink Manager family.

Features

  • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s.
  • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure.
  • Support for 3 egress fragmen.

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Datasheet preview – PM7389

Datasheet Details

Part number PM7389
Manufacturer PMC-Sierra
File Size 59.56 KB
Description Frame Engine and Datalink Manager
Datasheet download datasheet PM7389 Datasheet
Additional preview pages of the PM7389 datasheet.

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Full PDF Text Transcription

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Preliminary PM7389 FREEDM 84A1024 Frame Engine and Datalink Manager FEATURES • Single-chip multi-channel packet processor supporting a maximum aggregate bandwidth of 156 Mbit/s for line rate throughput transfers of packet sizes from 40 to 9.6 Kbytes, for up to an aggregate of 84 T1s, 63 E1s, or 3 DS-3s. • Provides simultaneous support of PPP, Frame Relay, Multilink-PPP and Multilink-Frame Relay protocols. Alternative protocols supported via HDLC termination and full packet store of the data within the HDLC structure. • Support for 3 egress fragmentation sizes (128, 256, and 512 bytes) configurable on a per multilink bundle. Optionally full packet transfers are supported on a per bundle basis. • Supports up to 42 multilink bundles with up to 12 member links per bundle.
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