PM7830 Datasheet | PMC-Sierra

OVERVIEW The PM7830 Baseband to Radio Interface Controller (BRIC) is a fullfeatured 6-port termination device that fully supports the CPRI specification for wireless base station interconnection. The BRIC provides integrated rate-adaptive SERDES links along with CPRI framing, mapping, switching, and bining functions. When used in conjunction with the 2-port PM7832 BRIC-2, the BRIC and BRIC-2 can be used to flexibly create scalable CPRI-pliant distributed architectures. - Supports up to 6 serial channels running independently at CPRI line rates from 614.4 Mbit/s to 2457.6 Mbit/s with 8B/10B-encoded data. - Supports up to 6 parallel Radio Bus Interfaces (RBIs) for output of user data. - Supports CPRI start-up sequence and link-rate auto-negotiation for both REC and RE operating modes. - Supports traffic switching at the CPRI Antenna Carrier (Ax C) level. - Supports IQ summing. - Supports multiplexing and termination of control and PRODUCT HIGHLIGHTS - Operates in all of the following Baseband-to-RF interconnect synchronization sub-channels: - - Up to 6 Ethernet Fast C&M channels. Up to 6 HDLC Slow C&M channels. topologies: - - - - - - - Measures round-trip delay on each CPRI link with an accuracy of Local interconnect using a central biner/distributor topology. Local interconnect using a full mesh topology. Remote interconnect using a point-to-point (P2P) star topology. Remote interconnect using a tree and branch topology. Remote interconnect using a chain topology. Remote interconnect using a ring topology. ±1 ns: - Provides programmable delay insertion to meet CPRI delay calibration requirements. - Supports serial line protection switching. - Supports configuration, control, monitoring and test capability on a per-channel basis. BLOCK DIAGRAM Clock Synthesis Unit (CSU) MPIF SYNC HDLC 6 x RMII/SMII JTAG Microprocessor Interface (MPIF) Synchronization & HDLC Processor (SCHP) JTAG Ctrl. & Mgmt. Processor (CMP) 6 x Tx Serial Link Data 6 x Rx Serial...