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PM8351 - 8-Channel 1.0-1.25 Gbps Transceiver

Download the PM8351 datasheet PDF. This datasheet also covers the PM8351_PMC variant, as both devices belong to the same 8-channel 1.0-1.25 gbps transceiver family and are provided as variant models within a single manufacturer datasheet.

General Description

The OctalPHYTM is an octal PHYsical layer transceiver ideal for systems requiring large numbers of point-to-point gigabit links.

It provides eight individual serial channels capable of operation at up to 1.25 Gbps, which may be grouped together to form a single 12.5 Gbps bidirectional link.

Key Features

  • Eight independent 1.0-1.25 Gbit/s transceivers.
  • Ultra low power operation: 1.25 Watts typical.
  • Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic.
  • Physical Coding Sublayer (PCS) logic for Gigabit Ethernet.
  • Optional receive FIFO which synchronizes incoming data to local clock domain.
  • Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PM8351_PMC-SierraInc.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number PM8351
Manufacturer PMC-Sierra
File Size 111.23 KB
Description 8-Channel 1.0-1.25 Gbps Transceiver
Datasheet download datasheet PM8351 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
PMC-Sierra,Inc. PM8351 OctalPHY™ 8-Channel 1.0-1.25 Gbps Transceiver FEATURES • Eight independent 1.0-1.25 Gbit/s transceivers • Ultra low power operation: 1.25 Watts typical • Integrated serializer/deserializer, clock synthesis, clock recovery, and 8B/10B encode/decode logic • Physical Coding Sublayer (PCS) logic for Gigabit Ethernet • Optional receive FIFO which synchronizes incoming data to local clock domain • Dual Data Rate (DDR) parallel interface with clock forwarding to halve ASIC terminal count and simplify timing • Extensive control of loopback, BIST, and operating modes via 802.3 compliant MDC/MDIO serial interface • Built-in packet generator/checker • “Trunking” feature to de-skew and align received parallel data across eight channels • IEEE 1149.