P1750AE-SOS Datasheet | PYRAMID

FEATURES Implements the MIL-STD-1750A Instruction Set Architecture Single Chip MIL-STD-1750AE Processor Form-Fit-Functionally patible with the P1750A CMOS Processor DAIS Instruction Mix Execution Performance Including Floating Point Arithmetic 1.8 MIPS at 20 MHz 2.25 MIPS at 25 MHz 2.7 MIPS at 30 MHz BIF Instructions Allow for High Throughput Implementations of Transcedental Functions, Navigational Algorithms, and DSP Functions 20, 25 and 30 MHz Operation over the Military Temperature Range (-55 to +125°c) Extensive Error and Fault Management and Interrupt Handling Capability. Built in Self Test. Two programmable Timers 26 User Accessible Registers TTL Signal Level patible Inputs and Outputs Single 5V ± 10% Power Supply Multiprocessor and Co-processor Capability Available in: - 68-Lead Quad Pack (Leaded Chip Carrier) Space Radiation Tolerant - Absolute latch up immunity - Total Dose: > 100K Rad/Si - SEU Tolerance <...