FEATURES
High Speed (Equal Access and Cycle Times) — 10/12/15/20 ns (Commercial) — 12/15/20 ns (Industrial) Low Power — 325 mW (max.) Single 3.3V ± 0.3V Power Supply Easy Memory Expansion Using CE and OE Inputs DESCRIPTION
Inputs are fully TTL-compatible. Access times as fast as 10 nanoseconds permit greatly enhanced system operating speeds. CMOS is utilized to reduce power consumption to a low level. The P3C1021 is a member of a family of PACE RAM™ products offering fast access times. FUNCTIONAL BLOCK DIAGRAM Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Fast tOE Automatic Power Down when deselected Packages —44-Pin SOJ, TSOP II The P3C1021 device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A15. Reading is accomplished by device selection (CE and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins.
PYRAMID
