Datasheet4U Logo Datasheet4U.com

P4C150 - ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM

Datasheet Summary

Description

The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications.

Features

  • Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times).
  • 10/12/15/20/25 ns (Commercial).
  • 15/20/25/35 ns (Military) Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved).
  • 24-Pin 300 mil DIP.
  • 24-Pin 300 mil SOIC.
  • 28-Pin LCC (350 x 550 mils).
  • 24-Pin.

📥 Download Datasheet

Datasheet preview – P4C150

Datasheet Details

Part number P4C150
Manufacturer PYRAMID
File Size 210.06 KB
Description ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM
Datasheet download datasheet P4C150 Datasheet
Additional preview pages of the P4C150 datasheet.
Other Datasheets by PYRAMID

Full PDF Text Transcription

Click to expand full text
P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK DESCRIPTION The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times.
Published: |