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P4C150 Datasheet PDF

PYRAMID P4C150

The P4C150 is a 4,096-bit ultra high-speed static RAM organized as 1K x 4 for high speed cache applications. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times.
Part No. P4C150
Datasheet P4C150 Download
Manufacturer
PYRAMID
Description ULTRA HIGH SPEED 1K x 4 RESETTABLE STATIC CMOS RAM
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P4C150 datasheet page 1 preview

FEATURES

Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) – 10/12/15/20/25 ns (Commercial) – 15/20/25/35 ns (Military) Chip Clear Function Low Power Operation Single 5V ± 10% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) – 24-Pin 300 mil DIP – 24-Pin 300 mil SOIC – 28-Pin LCC (350 x 550 mils) – 24-Pin CERPACK

DESCRIPTION

Inputs and outputs are fully TTLcompatible. The RAM operates from a single 5V ± 10% tolerance power supply. Access times as fast as 10 nanoseconds are available permitting greatly enhanced system operating s
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